Clock signals are used in virtually every integrated circuit (IC) and electronic system to control timing. For example, every time a rising edge occurs on a clock signal, all the flip-flops in a circuit might change state. Therefore, clock signals are often distributed widely throughout an IC or system. When a clock signal is widely distributed, inherent delays often cause various portions of the IC or system to receive the clock signal at different times. Further, setup and hold requirements can vary between different destination circuits. For these and other reasons, it is often desirable to perform a phase adjustment on a clock signal.
Phase adjustments are typically performed using a phase-lock loop (PLL) or delay-lock loop (DLL) circuit. However, PLLs are analog in nature and take a long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are difficult to design, and often are not feasible in a given circuit or system. DLLs can also be complicated and difficult to design. Additionally, DLLs typically consume a great deal of silicon area. Therefore, clock phase adjustment is often not feasible using known circuits and methods.
Therefore, it is desirable to provide circuits and methods that enable a circuit designer to adjust the phase of an input clock signal without using a PLL or DLL, using a fairly simple circuit that consumes a relatively small amount of silicon area. Preferably, such circuits and methods can optionally be implemented using the logic resources included in a programmable logic device (PLD).